Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time PLC increases with the number inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field gate array (FPGA) is more suitable than for high speed applications. executes instructions represented through LD. programmers are not familiar FPGA programming. But, does support LD based This work has developed application software to generate equivalent VerilogHDL code using LabVIEW. Novelty this each rung defined an "assign" statement which helps simultaneous execution all rungs. A data acquisition system was created monitor digital signals handled by FPGA. The verified a case study substances mixing traffic light control system.